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1 isl97673 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright intersil americas inc. 2010, 2012. all rights reserved all other trademarks mentioned are the property of their respective owners. 6-channel smbus or pwm dimming led driver with phase shift control isl97673 the isl97673 is a 6-channel 45v dual dimming capable led driver that can be used with either smbus/i 2 c or pwm signal for dimming control. the isl97673 drives 6 channels of led to support 78 leds from 4.5v to 26v or 48 leds from a boost supply of 2.7v to 26v and a separate 5v bias on the isl97673 vin pin the isl97673 compensates fo r non-uniformity of the forward voltage drops in the led strings with its 6 voltage controlled-current source channels. its headroom control monitors the highest led forward voltage string for output regulation, to minimize the voltage headroom and power loss in a typical multi-string operation. the isl97673 features optional channel phase shift control to minimize the input, output ripple characteristics and load transients as well as spreading the light output to help reduce the video and audio interference from the backlight driver operation. the phase shift can be programmed with equal phase angle or adjustable in 7-bit resolution. the isl97673 has a full range of dimming capabilities that include smbus/i 2 c controlled pwm dimming or dc dimming. another key feature of the isl97673 is that it allows very linear pwm dimming from 0.4% to 100% of up to 30khz. current matching of 0.4% to 100% dimming achieves 1% tolerance from 100hz to 5khz dimming and 3% tolerance from 5khz to 30khz dimming. features ? 6 channels ? 4.5v to 26.5v input ?45v output max ? up to 40ma led current per channel ? extensive dimming control -pwm/dpst dimming, i 2 c 8-bit with equal phase shift, and 0.007% direct pwm dimming at 200hz ? optional master fault protection ? pwm dimming linearity 0.4%~100% <30khz ? 600khz/1.2mhz selectable switching frequency ? dynamic headroom control ? protections with flag indication - string open/short circuit, v out short circuit, overvoltage and over-temperature protections - optional master fault protection ? current matching 0.7% ? 20 ld 4mmx3mm qfn package applications ? notebook displays wled or rgb led backlighting ? lcd monitor led backlighting ? automotive displays led backlighting typical application circuit smbdat(sda)/ v in = 4.5~26.5v en/pwm comp vin fault ovp fpwm v out = 45v*, 40ma per channel vdc smbclk(scl)/sel2 ch0 ch3 ch2 ch4 ch5 sel1 2 4 7 6 3 8 5 15 14 13 12 11 10 16 1 18 lx 20 pgnd 19 agnd 9 isl97673 ch1 rset 17 _flag *v in > 12v figure 1. isl97673 typical application diagram october 5, 2012 fn7633.2 n o t re co m m e nde d f o r ne w d e s i g ns re co m m e nd e d re p l ace m e nt p art s i s l 9 7 6 7 1 a o r i s l 9 7 6 7 2 b
isl97673 2 fn7633.2 october 5, 2012 block diagram 45v*, 25ma per string 78 (6x13) leds ref gen smbclk(scl) smbdat(sda) vin gm amp comp + - + - ch0 ch5 vin = 4.5v~26v logic fet drivers ovp reg lx isl97673 osc & ramp comp =0 imax ilimit smbus/ i2c control fault/status register highest vf string detect vdc temp sensor fault/status register fpwm dimming controller en/pwm pgnd rset + - gnd vin reg fault/status register o/p short ref_ovp ref_vsc bias + - dac0 pw m 0 controls 10uh/3a 4.7uf/50v ch1 pe open ckt, short ckt detects dac1 pwm1 controls dac5 pw m5 controls ext pwm control ckt 0 1 dac5 dac1 dac0 fault /status control ovp 5 pwm5 pwm1 pwm0 vset boost sw fsw dimming mode selection sel1 sel2 phase shift controller fault * vin > 6v figure 2. isl97673 block diagram 40ma *v in > 12v
isl97673 3 fn7633.2 october 5, 2012 pin configuration isl97673 (20 ld qfn) top view ordering information part number (notes 1, 2) part marking package (pb-free) pkg. dwg. # isl97673irz 7673 20 ld 4x3 qfn l20.3x4 ISL97673IRZ-EVAL evaluation board notes: 1. add ?-t? or ?-tk? suffix for tape and reel. please refer to tb347 for details on reel specifications. 2. these intersil pb-free plastic packaged products employ special pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is ro hs compliant and compatible with both snpb and pb-free so ldering operations). intersil pb-free products are msl classi fied at pb-free peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. 3. for moisture sensitivity level (msl), please see device information page for isl97673 . for more information on msl please see techbrief tb363 . lx pgnd comp rset smbclk(scl)/sel2 fpwm agnd ch0 fault vin en/pwm vdc sel1 smbdat(sda) ovp ch5 ch4 ch3 ch2 ch1 1 2 3 4 5 6 16 15 14 13 12 11 20 19 18 17 78910 /_flag pin descriptions (i = input, o = output, s = supply) pin name pin number type description fault 1 o fault disconnect switch vin 2 s input voltage for th e device and led power en/pwm 3 i dual functions: enable pin and pw m brightness control pin or dpst control input. the device needs 4ms for initia l power-up enable, then this pin can be applied with a pwm signal with off time no longer than 28ms. vdc 4 s de-couple capacitor for in ternally genera ted supply rail. sel1 5 i mode select pin 1 smbdat(sda)/_flag 6 i/o when sel1 is high, this pin is configured as the smbus/i 2 c serial data input/output. when sel1 is low or floating, this pin is configured as the fault flag output and will be pulled low when a fault co ndition occurs. an external pull-up is required. smbclk(scl)/sel2 7 i when sel1 is high, th is pin is configured as the smbus/i 2 c serial clock input. when sel1 is low or floati ng, this pins is configured as mode select pin 2, and operates in conjunction with se l1 to determine th e operating mode. see table 1 for details. fpwm 8 i pwm dimming frequency set pin with rfpwm agnd 9 s analog ground for precision circuits ch0, ch1, ch2, ch3, ch4, ch5 10, 11, 12, 13, 14, 15 i input 0, input 1, input 2, input 3, input 4, input 5 to current source, fb, and monitoring ovp 16 i overvoltage protection input rset 17 i resistor connection for setting led current, (see equation 2 for calculating the iledpeak) comp 18 o boost compensation pin pgnd 19 s power ground lx 20 o input to boost switch
isl97673 4 fn7633.2 october 5, 2012 table of contents typical application circuit .............................. 1 block diagram ................................................ 2 pin descriptions ............................................. 3 absolute maximum ratings ............................ 5 thermal information ...................................... 5 operating conditions ...................................... 5 electrical specifications ...............................5 typical performance curves ........................... 8 theory of operation........................................ 11 pwm boost converter .....................................11 enable and pwm ............................................11 ovp and v out requirement .............................11 current matching and current accuracy ............11 dynamic headroom control .............................11 operating modes ............................................11 dimming controls ..........................................12 maximum dc current setting .................. 12 dc current adjustment .......................... 12 pwm control ......................................... 12 pwm dimming frequency adjustment ...............13 phase shift control ................................ 13 switching frequency.......................................14 5v low dropout regulator...............................14 in-rush control and soft-start..........................14 fault protection and monitoring ........................14 short circuit protection (scp) ..........................14 open circuit protection (ocp) ..........................15 overvoltage protection (ovp) .......................... 15 undervoltage lockout .................................... 15 input overcurrent protection........................... 15 over-temperature protection (otp) ................. 15 write byte ........................................................ 18 read byte ........................................................ 18 slave device address......................................... 18 smbus/i2c register definitions ....................... 18 pwm brightness control register (0x00)........... 20 device control register (0x01)........................ 20 fault/status register (0x02) ........................... 21 si revision register (0x03) ............................. 21 dc brightness control register (0x07) ............. 22 configuration register (0x08) ......................... 22 output channel select and fault readout register (0x09) ........................................... 23 phase shift control register (0x0a) ................. 24 components selections ...................................24 input capacitor ............................................. 24 inductor ....................................................... 24 output capacitors.......................................... 25 output ripple................................................ 25 schottky diode.............................................. 25 applications ....................................................25 high current applications ............................... 25 multiple drivers operation .............................. 26 revision history ..............................................26 products..........................................................26 package outline drawing ................................ 27
isl97673 5 fn7633.2 october 5, 2012 absolute maximum ratings (t a = +25c) thermal information vin, en/pwm. . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 28v fault . . . . . . . . . . . . . . . . . . . . . vin - 8.5v to vin + 0.3v vdc, comp, rset, fpwm, ovp. . . . . . . . . . . . -0.3v to 5.5v smbclk(scl), smbdat(sda) . . . . . . . . . . . . -0.3v to 5.5v ch0 - ch5, lx . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 45v pgnd, agnd . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +0.3v above voltage ratings are all with respect to agnd pin esd rating human body model (tested per jesd22-a114e) . . . . . 3kv machine model (tested per jesd22-a115-a) . . . . . . . 300v charged device model . . . . . . . . . . . . . . . . . . . . . . . 1kv operating conditions temperature range . . . . . . . . . . . . . . . . . . -40c to +85c thermal resistance (typical) ja (c/w) jc (c/w) 20 ld qfn package (notes 4, 5, 7) . 40 2.5 thermal characterization (typical) psi jt (c/w) 20 ld qfn package (note 6) . . . . . . . . . . . . 1 maximum continuous junction temperature . . . . . . +125c storage temperature . . . . . . . . . . . . . . . -65c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/pb-freereflow.asp important note: all parameters having min/ma x specifications are guaranteed. typical va lues are for informat ion purposes only. u nless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: t j = t c = t a caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 4. ja is measured in free air with the component mounted on a high effective thermal conductivity test board with ?direct attach? features. see tech brief tb379. 5. for jc , the ?case temp? location is the center of the exposed metal pad on the package underside. 6. psi jt is the psi junction-to-top thermal characterization parameter. if the package top temperature can be measured with this rating then the die junction temperature can be estimated more accurately than the jc and jc thermal resistance ratings 7. refer to jesd51-7 high effective thermal conductivity board layout for proper via and plane designs. electrical specifications all specifications below are tested at t a = +25c; v in = 12v, en/pwm = 5v, r set = 20.1k , unless otherwise noted. boldface limits apply over the operating temperature range, -40c to +85c. parameter description condition min (note 8) typ max (note 8) unit general v in (note 9) backlight supply voltage 11 leds per channel (3.2v/20ma type) 4.5 26.5 v i vin_stby vin shutdown current 10 a v out output voltage 4.5v < v in 26v, f sw = 600khz 45 v 8.55v < v in 26v, f sw = 1.2mhz 45 v 4.5v < v in 8.55v, f sw = 1.2mhz v in /0.19 v v uvlo undervoltage lock-out threshold 2.6 3.3 v v uvlo_hys undervoltage lock-out hysteresis 275 mv regulator v dc ldo output voltage v in > 6v 4.55 4.8 5 v i vdc_stby standby current en/pwmi = 0v 5 a i vdc active current en/pwmi = 5v 5 ma v ldo vdc ldo droop voltage v in > 5.5v, 20ma 20 200 mv en low guaranteed range for en input low voltage 0.5 v en hi guaranteed range for en input high voltage 1.8 v t enlow en/pwmi low time before shut-down 30.5 ms
isl97673 6 fn7633.2 october 5, 2012 boost sw ilimit boost fet current limit 1.5 2.0 2.7 a r ds(on) internal boost switch on-resistance t a = +25c 235 300 m ss soft-start 100% led duty cycle 7 ms eff_peak peak efficiency v in = 12v, 72 leds, 20ma each, l = 10h with dcr 101m , t a = +25c 92.9 % v in = 12v, 60 leds, 20ma each, l = 10h with dcr 101m , t a = +25c 90.8 % i out / v in line regulation 0.1 % d max boost maximum duty cycle fsw = 1, 600khz 90 % fsw = 0, 1.2mhz 81 d min boost minimum duty cycle fsw = 1, 600khz 9.5 % fsw = 0, 1.2mhz 17 f osc_hi lx frequency high fsw = 1, 600khz 475 600 640 khz f osc_lo lx frequency low fsw = 0, 1.2mhz 0.97 1.14 1.31 mhz ilx_leakage lx leakage current lx = 45v, en = 0 10 a fault detection v sc short circuit threshold accuracy reg0x08, sc[1:0] = 01 3.15 3.6 4.3 v reg0x08, sc[1:0] = 10 4.2 4.8 5.4 v reg0x08, sc[1:0] = 11 5.2 5.85 6.6 v temp_shtdwn temperature shutdown threshold 150 c temp_hyst temperature s hutdown hysteresis 23 c v ovplo overvoltage limit on ovp pin 1.19 1.25 v ovp fault ovp short detection fault level 400 mv current sources i match dc channel-to-channel current matching r set = 20.1k , reg0x00 = 0xff (i out = 20ma) 0.7 1.0 % i acc current accuracy -1.5 +1.5 % v headroom dominant channel current source headroom at fbx pin i led = 20ma t a = +25c 500 mv v rset voltage at rset pin r set = 20.1k 1.2 1.22 1.24 mv i ledmax maximum led current per channel v in = 12v, v out = 45v, fsw=1.2mhz, t a = +25c 40 ma pwm generator vil guaranteed range for pwmi input low voltage 0.8 v vih guaranteed range for pwmi input high voltage 1.5 vdd v fpwm pwmi input frequency range 200 30,000 hz pwmacc pwm input accuracy 8bits electrical specifications all specifications below are tested at t a = +25c; v in = 12v, en/pwm = 5v, r set = 20.1k , unless otherwise noted. boldface limits apply over the operating temperature range, -40c to +85c. (continued) parameter description condition min (note 8) typ max (note 8) unit
isl97673 7 fn7633.2 october 5, 2012 fpwm pwm dimming frequency range rfpwm = 660k 90 100 110 hz tdirectpwm direct pwm minimum on time direct pwm mode 250 350 ns fault pin i fault fault pull-down current v in = 12v 12 21 30 a v fault fault clamp voltage with respect to v in v in = 12v, v in - v fault 6 7 8.3 v lxstart_thres lx start-up threshold 1.3 1.4 1.5 v ilxstart-up lx start-up current 1 3.5 5 ma smbus/i 2 c interface logic level v il guaranteed range for data, clock input low voltage 0.8 v vih guaranteed range for data, clock input high voltage 1.5 vdd v v ol smbus/i 2 c output data line logic low voltage i pullup = 4ma 0.17 v i leak input leakage on smbdata/smbclk measured at 4.8v -10 10 a smbus/i 2 c timing specifications (note 10) ten-smb/i 2 c minimum time between en high and smbus/i 2 c enabled 1f capacitor on vdc 2 ms pws pulse width suppression on smbclk/smbdat 0.15 0.45 s f smb smbus clock frequency 400 khz t buf bus free time between stop and start condition 1.3 s t hd:sta hold time after (repeated) start condition. after this period, the first clock is generated 0.6 s t su:sta repeated start condition setup time 0.6 s t su:sto stop condition setup time 0.6 s t hd:dat data hold time 300 ns t su:dat data setup time 100 ns t low clock low period 1.3 s t high clock high period 0.6 s t f clock/data fall time 300 ns t r clock/data rise time 300 ns notes: 8. parameters with min and/or max limits are 100% tested at + 25c, unless otherwise specified. temperature limits established by characterization and are not production tested. 9. independent from the numbers of leds, at minimum v in of 4.5v, maximum v out is limited to 35v. and at maximum v in of 26.5v, minimum v out is limited 28v. 10. limits established by characterizat ion and are not production tested. electrical specifications all specifications below are tested at t a = +25c; v in = 12v, en/pwm = 5v, r set = 20.1k , unless otherwise noted. boldface limits apply over the operating temperature range, -40c to +85c. (continued) parameter description condition min (note 8) typ max (note 8) unit
isl97673 8 fn7633.2 october 5, 2012 typical performance curves figure 3. efficiency vs up to 20ma led current (100% led duty cycle) vs v in figure 4. efficiency vs up to 30ma led current (100% led duty cycle) vs v in figure 5. efficiency vs v in vs switching frequency at 20ma (100% led duty cycle) figure 6. efficiency vs v in vs switching frequency at 30ma (100% led duty cycle) figure 7. efficiency vs v in vs temperature at 20ma (100% led duty cycle) figure 8. channel-to-channel current matching 100 70 80 90 50 30 40 60 0 10 20 0 5 10 15 20 25 efficiency (%) i led(ma) 5v in 12v in 24v in 100 70 80 90 50 30 40 60 0 10 20 0 5 10 15 20 25 efficiency (%) i led(ma) 30 35 6p10s_30ma/channel 5v in 12v in 24v in 0 10 20 30 40 50 60 70 80 90 100 0 5 10 15 20 25 30 1.2mhz 580k efficiency (%) v in 0 5 10 15 20 25 efficiency (%) v in 30 1.2mhz 0 20 40 60 80 100 580k 0 10 20 30 40 50 60 70 80 90 100 0 5 10 15 20 25 30 +25c -40c 0c +85c efficiency (%) v in 0.40 0.10 0.20 0.30 -0.10 -0.20 0.00 012345 current matching(%) channel 6 -0.30 -0.40 7 21 v in 12 v in 4.5 v in
isl97673 9 fn7633.2 october 5, 2012 figure 9. current linearity vs low level pwm dimming duty cycle vs v in figure 10. v headroom vs v in at 20ma figure 11. v out ripple voltage, v in = 12v, 6p12s at 20ma/channel figure 12. in-rush and led current at v in = 6v for 6p12s at 20ma/channel figure 13. in-rush and led current at v in = 12v for 6p12s at 20ma/channel figure 14. line regulation with v in change from 6v to 26v, v in = 12v, 6p12s at 20ma/channel typical performance curves (continued) 0 0.2 0.4 0.6 0.8 1.0 1.2 01 4 dc 23 56 current 4.5 v in 12 v in 0.40 0.45 0.50 0.55 0.60 0 5 10 15 20 25 30 v headroom (v) -40c 0c +25c v in (v)
isl97673 10 fn7633.2 october 5, 2012 figure 15. line regulation with v in change from 26v to 6v for 6p12s at 20ma/channel figure 16. load regulation with i led change from 0% to 100% pwm dimming, v in = 12v, 6p12s at 20ma/channel figure 17. load regulation with i led change from 100% to 0% pwm dimming, v in = 12v, 6p12s at 20ma/channel figure 18. isl97671 shuts down and stops switching ~ 30ms after en goes low typical performance curves (continued)
isl97673 11 fn7633.2 october 5, 2012 theory of operation pwm boost converter the current mode pwm boost converter produces the minimal voltage needed to enable the led stack with the highest forward voltage drop to run at the programmed current. the isl97673 employs current mode control boost architecture that has a fast current sense loop and a slow voltage feedback loop. such architecture achieves a fast transient response that is essential for the notebook backlight application where the power can be a series of drained batteries or instantly change to an ac/dc adapter without rendering a noticeable visual nuisance. the number of leds that can be driven by isl97673 depend on the type of led chosen in the application. the isl97673 are capable of boosting up to 45v and typically driving 13 leds in series for each of the 6 channels, enabling a total of 104 pieces of the 3.2v/20ma type of leds. enable and pwm the isl97673 has en/pwm pin that serves dual purposes; it is used as an enable signal and can be used as a pwm input signal for dimming. if a pwm signal is applied to this pin, the first pulse of minimum 4ms will be used as an enable signal. if there is no signal for longer than 28ms, the device will enter shutdown. ovp and v out requirement the overvoltage protection (ovp) pin has a function of setting the overvoltage trip level as well as limiting the v out regulation range. the isl97673 ovp threshold is set by r upper and r lower as shown in equation 1: v out can only regulate between 64% and 100% of the v out _ ovp such that: allowable v out = 64% to 100% of v out _ ovp for example, if 10 leds are used with the worst case v out of 35v. if r 1 and r 2 are chosen such that the ovp level is set at 40v, then the v out is allowed to operate between 25.6v and 40v. if the requirement is changed to a 6 leds 21v v out application, then the ovp level must be reduced and users should follow v out = (64% ~100%) ovp requirement. otherwise, the headroom control will be disturbed such that the channel voltage can be much higher than expected and sometimes it can prevent the driver from operating properly. the ratio of the ovp capacitors should be the inverse of the ovp resistors. for example, if r upper /r lower = 33/1, then c upper /c lower = 1/33 with c upper = 100pf and c lower = 3.3nf. current matching an d current accuracy each channel of the led current is regulated by the current source circuit, as shown in figure 19. the led peak current is set by translating the r set current to the output with a scaling factor of 410.5/r set . the source terminals of the current source mosfets are designed to run at 500mv to optimize power loss versus accuracy requirements. the sources of errors of the channel-to-channel current matching come from the op amps offset, internal layout, reference, and current source resistors. these parameters are optimized for current matching and absolute current accuracy. however, the absolute accuracy is additionally determined by the external r set . a 1% tolerance resistor is recommended. dynamic headroom control the isl97673 features a prop rietary dynamic headroom control circuit that detects the highest forward voltage string or effectively the lowest voltage from any of the ch0-ch5 pins digitally. when the lowest channel voltage is lower than the short circuit threshold, v sc , such voltage will be used as the feedback signal for the boost regulator. the boost makes the output to the correct level such that the lowest channel is at the target headroom voltage. since all led stacks are connected to the same output voltage, the other channel pins will have a higher voltage, but the regulated current source circuit on each channel will ensure that each channel has the same current. the output voltage will regulate cycle-by- cycle and it is always referenced to the highest forward voltage string in the architecture. operating modes the isl97673 has extensive operating modes such as smbus controlled pwm or dc dimmings, pwm dimming with phase shift control and more. depending on the pin 5 (sel1) condition, pins 6 and 7 correspond to different operating modes as shown in table 1. v out_ovp 1.21v r upper r lower + () r lower ? = (eq. 1) figure 19. simplified current source circuit ref + - + - pwm dimming rset + dc dimming ref + - + - rset -
isl97673 12 fn7633.2 october 5, 2012 ? when sel1 is high, pins 6 and 7 correspond to smbdat and smbclk accordingly. the dimming duty cycle is controlled by the smbus/i 2 c communications and the dimming frequency is set by rfpwm. ? when sel1 is floating and sel2 is high, the channels will be in phase shift mode with fixed delay. the dimming signal is derived from the applied pwmi signal and the dimming frequency is set by rfpwm. ? when sel1 is floating and sel2 is floating, the channels will be in phase shift mode with equal phase. the dimming signal is derived from the applied pwmi signal and the dimming frequency is set by rfpwm. ? when sel1 is floating and sel2 is low, the channels phase shift mode is disabled. the dimming signal is derived from the applied pwmi signal and the dimming frequency is set by rfpwm. ? when sel1 is low and sel2 is high, this combination is not used thus the operation will not change. ? when sel1 is low and sel2 is floating, it is in dc dimming mode such that the output current is averaged in dc and is proportional to the applied pwmi signal duty cycle. ? when sel1 is low an d sel2 is low, it is in direct pwm mode such that the dimming follows directly from the applied pwmi signal. dimming controls the isl97673 allow two ways of controlling the led current, and therefore, the brightness. they are: 1. dc current adjustment 2. pwm chopping of the led current defined in step 1. there are various ways to achieve dc or pwm current control, which will be described in the following. maximum dc current setting the initial brightness should be set by choosing an appropriate value for r set . this should be chosen to fix the maximum possible led current: dc current adjustment once r set is fixed, the led dc current can be adjusted through register 0x07 (brtdc) as equation 3: brtdc can be programmed from 0 to 255 in decimal and defaults to 255 (0xff). if left at the default value, led current will be fixed at i ledmax . brtdc can be adjusted dynamically on the fly during operation and a ?0? value disconnects all channels. for example, if the maxi mum required led current (i led(max) ) is 20ma, rearranging equation 2 yields equation 4: if brtdc is set to 200 then: pwm control the isl97673 provides two different pwm dimming methods, as described in the following. each of these methods results in pwm chopping of the current in the leds for all 6 channels to provide an average led current. during the on periods, the led current will be defined by the value of r set and brtdc, as described in equations 2 and 3. the source of the pwm signal can be described as follows: 1. smbus/i 2 c generated 256 level duty cycle programmed through the smbus/i 2 c. 2. external signal from pwm. the default pwm dimming is in smbus/i 2 c mode. in both methods, the average led current of each channel is controlled by i led and the pwm duty cycle in percent as: method 1 (smbus/i 2 c controlled pwm) to use this mode, users need to set register 0x01 to 0x05 with en/pwm in logic high. the average led current of each channel is controlled by the smbus/i 2 c setting as: where brt is the pwm brightness level programmed in the register 0x00. brt ranges from 0 to 255 in decimal and defaults to 255 (0xff). brt = 0 disconnects all channels. table 1. sel1 sel2 operating mode high n/a selectable by smbus/i 2 c interface float high pwmi, fixed-delay phase shift pwm float float pwmi, equal-phase phase shift pwm float low pwmi, no-delay pwm low high not used low float dc current adjustment low low direct pwm i ledmax 410.5 () r set ------------------- = (eq. 2) i led 1.58x brtdc r set ? () = (eq. 3) r set 410.5 0.02 ? 20.52k == (eq. 4) i led 1.58 200 20100 15.7ma = ? ? = (eq. 5) i led ave () i led pwm = (eq. 6) i led ave () i led brt 255 ? () = (eq. 7)
isl97673 13 fn7633.2 october 5, 2012 method 2 (external applied pwm) to use this mode users need to set register 0x01 to 0x03 the average led current of each channel can also be controlled by an external pwm signal as equation 8: pwm dimming frequency adjustment (applicable to smbus/i 2 c controlled pwm and dpst modes) except for the external pwm dimming mode, the dimming frequencies of any other modes are set by an external resistor at the fpwm pin as equation 9: where f pwm is the desirable pwm dimming frequency and r fpwm is the setting resistor. the pwm dimming frequency can be set or applied up to 30khz with duty cycle from 0.4% to 100%. phase shift control the isl97673 is capable of delaying the phase of each current source to minimize load transients. by default, phase shifting is disabled as shown in figure 20 where the channels pwm currents are switching uniformly. the duty cycles can be controlled by the data in pwm brightness control register via the smbus/i 2 c interface, an external pwm signal with the frequency set by the rfpwm, or by an external pwm signal with the frequency set by the incoming signal. when equalphase = 1, the phase shift evenly spreads the channels switching across the pwm cycle, depending on how many channels are enabled, as shown in figures 21 and 22. equal phase means there are fixed delays between channels and such delay can be calculated as equations 10 and 11: where (255/n) is rounded down to the nearest integer. for example, if n = 6, (255/n) = 42, that leads to: t d1 = t fpwm x 42/255 t d2 = t fpwm x 45/255 where t fpwm is the sum of t on and t off . n is the number of led channels. the isl976 73 will detect the numbers of operating channels automatically. i liled ave () i led pwm = (eq. 8) f pwm 6.66 7 10 rfpwm ----------------------- - = (eq. 9) figure 20. no delay (default phase shift disabled) iled0 iled1 iled2 iled3 iled4 iled5 t on t off t fpwm figure 21. 6 equal phas e channels phase shift illustration iled0 iled1 iled2 iled3 iled4 iled5 iled0 t on t off pwmi 60% 40% t fpwm 60% 40% t d1 t d1 t d1 t d1 t d1 t d2 figure 22. 4 equal phas e channels phase shift illustration iled1 iled2 iled3 iled4 iled1 t on t off pwmi 60% 40% 60% 40% t d1 t d1 t d1 t d2 t fp w m (t pwmout ) t pw min t d1 = fixed delay with integer only while the decimal value will be discarded (eg. 63.75=63) t d1 t fpwm 255 ------------------ - x 255 n --------- - ?? ?? = (eq. 10) t d2 t fpwm 255 ------------------ - x 255 n 1 ? () 255 n --------- - ?? ?? ? ?? ?? = (eq. 11)
isl97673 14 fn7633.2 october 5, 2012 the isl97673 allows the user to program the amount of phase shift degree in 7-bit resolution, as shown in figure 24. to enable programmable phase shifting, the user must write to the phase shift control register with equalphase = 0 and the desirable phase shift value of phaseshift[6:0]. the delay between ch5 and the repeated ch0 is the rest of the pwm cycle. switching frequency there are 2 levels of switching frequencies enable for the boost regulator?s control of the lx pin: 600khz or 1.2mhz. each can be programmed in the configuration register 0x08 bit 2. the default switching frequency is at 600khz. 5v low dropout regulator a 5v ldo regulator is present at the vdc pin to develop the necessary low voltage supply, which is used by the chips internal control circuitry. because vdc is an ldo pin, it requires a bypass capacito r of 1f or more for the regulation. low input voltage also allows only lower output voltage applications only with the maximum boost ratio defined in ?components selections? on page 24. the vdc pin can be us ed as a coarse reference with a few ma sour cing capability. in-rush control and soft-start the isl97673 has separately built in independent in-rush control and soft-start functions. the in-rush control function is built around the short circuit protection fet, and is only available in applications, which include this device. at start-up, the fault protection fet is turned on slowly due to a 15a pull-down current output from the fault pin. this discharges the fault fet's gate-source capacitance, turning on the fet in a controlled fashion. as this happens, the output capacitor is charged slowly through the weakly turned on fet before it becomes fully enhanced. this results in a low in-rush current. this current can be further reduced by adding a capacitor (in the 1nf to 5nf range) across the gate-source terminals of the fet. once the chip detects that the fault protection fet is turned on hard, it is assumed that in-rush has completed. at this point, th e boost regulator will begin to switch and the current in the inductor will ramp-up. the current in the boost power switch is monitored and the switching is terminated in any cycle where the current exceeds the current limit. the isl97673 includes a soft-start feature where this current limit starts at a low value (275ma). this is stepped up to the final 2.2a current limit in 7 further st eps of 275ma. these steps will happen over at least 8ms, and will be extended at low led pwm frequencies if the led duty cycle is low. this allows the output capacitor to be charged to the required value at a low current limit and prevents high input current for systems that have only a low to medium output current requirement. for systems with no master fault protection fet, the inrush current will flow towards c out when vin is applied and it is determined by the ramp rate of vin and the values of c out and l. fault protection and monitoring the isl97673 features extensive protection functions to cover all the perceivable failure conditions. the failure mode of a led can be either open circuit or as a short. the behavior of an open ci rcuited led can additionally take the form of either infinite resistance or, for some leds, a zener diode, which is integrated into the device in parallel with the now opened led. for basic leds (which do not have built-in zener diodes), an open circuit failure of an led will only result in the loss of one channel of leds without affecting other channels. similarly, a short circuit condition on a channel that results in that channel being turned off does not affect other channels unless a similar fault is occurring. led faults are reported via the smbus/i 2 c interface to register 0x02 (fault/status register). the controller is able to determine which channels have failed via register 0x09 (output masking register). the controller can also choose to use register 0x09 to disable faulty channels at start-up, resulting in only further faulty channels being reported by register 0x02. due to the lag in boost response to any load change at its output, certain transient events (such as led current steps or significant step changes in led duty cycle) can transiently look like led fault modes. the isl97673 uses feedback from the leds to determine when it is in a stable operating region and prevents apparent faults during these transient events from allowing any of the led stacks to fault out. see table 2 for more details. a fault condition that results in high input current due to a short on v out will result in a shutdown of all output channels. the control device logic will remain functional such that the fault/status register can be interrogated by the system. the root cause of the failure will be loaded to the volatile fault/status register so that the host processor can interrogate the data for failure monitoring. short circuit protection (scp) the short circuit detection circuit monitors the voltage on each channel and disables faulty channels which are detected above the programmed short circuit threshold. figure 23. phase shift with 7-bit programmable delay iled0 iled1 iled2 iled3 iled4 iled5 t pd t pd t pd t pd t pd t on t off t fpwm
isl97673 15 fn7633.2 october 5, 2012 there are three selectable levels of short circuit threshold (3.6v, 4.8v, and 5.85v) that can be programmed through the configuration register 0x08. when an led becomes shorted, the action taken is described in table 2. the default short circuit threshold is 5.85v. the detection of this failure mode can be disabled via register 0x08. open circuit protection (ocp) when one of the leds becomes open circuit, it can behave as either an infinite resistance or a gradually increasing finite resistance. the isl97673 monitors the current in each channel such that any string which reaches the intended output current is considered ?good?. should the current subsequently fall below the target, the channel will be considered an ?open circuit?. furthermore, should the boost output of the isl97673 reaches the ovp limit or should the lower over-temperature threshold be reached, all channels which are not ?good? will immediately be considered as ?open circuit?. detection of an ?open circuit? channel will result in a time-out before disabling of the affected channel. this time-out is run when the device is above the lower over-temperature threshold in an attempt to prevent the upper over-temperature trip point from being reached. some users employ some special types of leds that have zener diode structure in parallel with the led for esd enhancement, thus enabling open circuit operation. when this type of led goes open circuit, the effect is as if the led forward voltage has increased, but no light is emitted. any affected string will not be disabled, unless the failure results in the boost ovp limit being reached, allowing all other leds in the string to remain functional. care should be taken in this case that the boost ovp limit and scp limit are set properly, so as to make sure that multiple failures on one string do not cause all other good channels to be faulted out. this is due to the increased forwar d voltage of the faulty channel making all other channel look as if they have led shorts. see table 2 for details for responses to fault conditions. overvoltage protection (ovp) the integrated ovp circuit monitors the output voltage and keeps the voltage at a safe level. the ovp threshold is set as: these resistors should be large to minimize the power loss. for example, a 1mk r upper and 30k r lower sets ovp to 41.2v. large ovp resistors also allow c out discharges slowly during the pwm off time. parallel capacitors should also be placed across the ovp resistors such that r upper /r lower = c lower /c upper . using a c upper value of at least 30pf is recommended. these capacitors reduce the ac impedance of the ovp node, which is important when using high value resistors. undervoltage lockout if the input voltage falls below the uvlo level of 2.45v, the device will stop switching and be reset. operation will restart only if the device is re-enabled through the smbus/i 2 c interface once the input voltage is back in the operating range. in non-smbus/i 2 c applications, the part will automatically restart once the input voltage clears the uvlo threshold with the part already enabled. input overcurrent protection during normal switching operation, the current through the internal boost power fet is monitored. if the current exceeds the current limit, the internal switch will be turned off. this monitoring happens on a cycle by cycle basis in a self protecting way. additionally, the isl97673 monitors the voltage at the lx and ovp pins. at startup, a fixed current is injected out of the lx pins and into the outp ut capacitor. the device will not start up unless the voltage at lx exceeds 1.2v. the ovp pin is also monitored such that if it rises above and subsequently falls below 20% of the target ovp level, the input protection fet will be switched off. over-temperature protection (otp) the isl97673 includes two over-temperature thresholds. the lower threshold is set to +130c. when this threshold is reached, any channel which is outputting current at a level below the regulation target will be treated as ?open circuit? and disabled after a time-out period. the intention of the lower threshold is to allow bad channels to be isolated and disabled before they cause enough power dissipation (as a result of other channels having large voltages across them) to hit the upper temperature threshold. the upper threshold is set to +150c. each time this is reached, the boost will stop switching and the output current sources will be switched off. hitting of the upper threshold will also set the thermal fault bit of the fault/status register 0x02. unless disabled via the en pin, the device stays in an active state throughout, allowing an external processor to interrogate the fault condition. for the extensive fault protection conditions, please refer to figure 24 and table 2 for details. ovp 1.21v r upper r lower + () r lower ? = (eq. 12)
isl97673 16 fn7633.2 october 5, 2012 figure 24. simplified fault protections q5 vsc ch5 vset dc current pwm/oc0/sc0 ref fet driver imax ilimit driver fault ovp vin t2 otp thrm shdn q0 vsc ch0 vout smb/i 2 c control logic fault/ status register vset pwm/oc5/sc5 temp sensor logic lx t1 otp thrm shdn o/p short + - + - reg vset/2 table 2. protections table case failure mode detection mode failed channel action good channels action v out regulated by 1 ch0 short circuit upper over-temperature protection limit (otp) not triggered and ch0 < 4v ch0 on and burns power. ch1 thro ugh ch5 normal highest vf of ch1 through ch5 2 ch0 short circuit upper otp triggered but vch0 < 4v all channels go off until chip cooled and then comes back on with current reduced to 76%. subsequent otp triggers will reduce i out further. same as ch0 highest vf of ch1 through ch5 3 ch0 short circuit upper otp not triggered but ch0 > 4v ch1 disabled after 6 pwm cycle time-out. ch1 through ch5 normal highest vf of ch1 through ch5 4 ch0 open circuit with infinite resistance upper otp not triggered and ch0 < 4v v out will ramp to ovp. ch1 will time-out after 6 pwm cycles and switch off. v out will drop to normal level. ch1 through ch5 normal highest vf of ch1 through ch5 5ch0 led open circuit but has paralleled zener upper otp not triggered and ch0 < 4v ch1 remains on and has highest vf, thus v out increases. ch1 through ch5 on, q1 through q5 burn power vf of ch0
isl97673 17 fn7633.2 october 5, 2012 6ch0 led open circuit but has paralleled zener upper otp triggered but ch0 < 4v all channels go off until chip cooled and then comes back on with current reduced to 76%. subsequent otp triggers will reduce i out further same as ch0 vf of ch0 7ch0 led open circuit but has paralleled zener upper otp not triggered but chx > 4v ch0 remains on and has highest vf, thus v out increases. v out increases, then ch-x switches off after 6 pwm cycles. this is an unwanted shut off and can be prevented by setting ovp at an appropriate level. vf of ch0 8 channel-to- channel vf too high lower otp triggered but chx < 4v any channel at below the target current will fault out after 6 pwm cycles. remaining channels driven with normal current. highest vf of ch0 through ch5 9 channel-to- channel vf too high upper otp triggered but chx < 4v all channels go off until chip cooled and then comes back on with current reduced to 76%. subsequent otp triggers will reduce i out further highest vf of ch0 through ch5 10 output led stack voltage too high v out > vovp any channel that is below the target current will time-out after 6 pwm cycles, and v out will return to the normal regulation voltage requir ed for other channels. highest vf of ch0 through ch5 11 v out /lx shorted to gnd at start-up or v out shorted in operation lx current and timing are monitored. ovp pins monitored for excursions below 20% of ovp threshold. the chip is permanently shut down 31ms after power-up if v out /lx is shorted to gnd. table 2. protections table (continued) case failure mode detection mode failed channel action good channels action v out regulated by figure 25. smbus/i 2 c interface v ih v il v ih v il t r t low t hd:sta t hd:dat t f t high t su:dat t su:sta s s p p t su:sto smbdat smbclk notes: smbus/i 2 c description s = start condition p = stop condition a = acknowledge a = not acknowledge r/w = read enable at high; write enable at low t buf
isl97673 18 fn7633.2 october 5, 2012 write byte the write byte protocol is only three bytes long. the first byte starts with the slave address followed by the ?command code,? which translates to the ?register index? being written. the third byte contains the data byte that must be written into the register selected by the ?command code?. a shaded label is used on cycles during which the slaved backlight controller ?owns? or ?drives? the data line. all other cycles are driven by the ?host master.? read byte as shown in the figure 27, the four byte long read byte protocol starts out with the slave address followed by the ?command code? which translates to the ?register index.? subsequently, the bus direction turns around with the re-broadcast of th e slave address with bit 0 indicating a read (?r?) cycle. the fourth byte contains the data being returned by th e backlight controller. that byte value in the data byte reflects the value of the register being queried at the ?command code? index. note the bus directions, wh ich are highlighted by the shaded label that is used on cycles during which the slaved backlight controller ?owns? or ?drives? the data line. all other cycles are dr iven by the ?host master.? slave device address the slave address contains 7 msb plus one lsb as r/w bit, but these 8 bits are usually called slave address bytes. as shown in figure 28, the high nibble of the slave address byte is 0x5 or 0101b to denote the ?backlight controller class.? bit 3 in the lower nibble of the slave address byte is 1. bit 0 is always the r/w bit, as specified by the smbus/i 2 c protocol. note: in this document, the device address will always be expressed as a full 8-bit address instead of the shorter 7-bit address typically used in other backlight controller specifications to avoid confusion. therefore, if the device is in the write mode where bit 0 is 0, the slave address byte is 0x58 or 01011000b. if the device is in the read mode where bit 0 is 1, the slave address byte is 0x59 or 01011001b. the backlight controller may sense the state of the pins at por or during normal operation. the pins will not change state while the device is in operation. smbus/i 2 c register definitions the backlight controller registers are byte wide and accessible via the smbus/i 2 c read/write byte protocols. their bit assign ments are provided in the following sections with reserved bits containing a default value of ?0?. figure 26. write byte protocol master to slave slave to master 171181811 sslave addressw a command code adata byte ap figure 27. read byte protocol master to slave slave to master 1711 8 11811811 s slave address w a command code a s slave address r a data byte a p figure 28. slave address byte definition device identifier device address r e a d / w r it e b it msb lsb 0101100r/w
isl97673 19 fn7633.2 october 5, 2012 table 3a. register listing address register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default value smbus/i 2 c protocol 0x00 pwm brightness control register brt7 brt6 brt5 brt4 brt3 brt2 brt1 brt0 0xff read and write 0x01 device control register reserved reserved reserved reserved reserved pwm_md pwm_sel bl_ctl 0x00 read and write 0x02 fault/status register reserved reserved 2_ch_sd 1_ch_sd bl_stat ov_curr thrm_shdn fault 0x00 read only 0x03 si revision register 1 1 0 0 1 rev2 rev1 rev0 0xc8 read only 0x07 dc brightness control register brtdc7 brtdc6 brtdc5 brtdc4 brtdc3 brtdc2 brtdc1 brtdc0 0xff read and write 0x08 configuration register reserved directpwm pwmtodc bstslew rate1 bstslew rate0 fsw vsc1 vsc0 0x1f read and write 0x09 output channel register reserved reserved ch5 ch4 ch3 ch2 ch1 ch0 0x3f read and write 0x0a phase shift deg equal phase phase shift6 phase shift5 phase shift4 phase shift3 phase shift2 phase shift1 phase shift0 0x00 read and write table 3b. data bit descriptions address register data bit descriptions 0x00 pwm brightness control register brt[7..0] = 256 steps of dpwm duty cycle brightness control 0x01 device control register pwm_md = pwm mode sele ct bit (1 = absolute brightness, 0 = % change), default = 0 pwm_sel = brightness control select bit (1 = control by pwmi, 0 = control by smbus/i 2 c), default = 0 bl_ctl = bl on/off (1 = on, 0 = off), default = 0 0x02 fault/status register 2_ch_sd = two led output channels are shutdown (1 = shutdown, 0 = ok) 1_ch_sd = one led output channel is shutdown (1 = shutdown, 0 = ok) bl_stat = bl status (1 = bl on, 0 = bl off) ov_curr = input overcurrent (1 = over current condition, 0 = current ok) thrm_shdn = thermal shutdown (1 = thermal fault, 0 = thermal ok) fault = fault occurred (logic ?or? of all of the fault conditions) 0x03 si revision register rev[2..0] = silicon rev (rev 0 through rev 7 allowed for silicon spins) 0x07 dc brightness control register brtdc[7..0] = 256 steps of dc brightness control 0x08 configuration register directpwm = forces the pwm in put signal to directly control the current sources. pwm-to-dc = switches current sources on and varies dc level rather than pwming. bstslewrate = controls strength of fet driver. 00 - 25% drive strength, 01 - 50% drive strength, 10 - 75% drive stre ngth, 11 - 100% drive strength. fsw = switching frequencies selection, fsw = 0 = 1.2mhz. fsw = 1 = 600khz vsc[1..0] = short circuit thresholds select ion, 0 = disabled, 1 = 3.6v, 2 = 4.8v, 3 = 5.8v 0x09 output channel select and fault readout register ch[5..0] = output channel read and writ e. in write, 1 = channel enabled, 0 = channel disabled. in read, 1 = channel ok, 0 = channel shutdown or disabled 0x0a phase shift degree equalphase = controls phase shift mode - when 0, ph ase shift is defined by phaseshift<6:0>. when 1, phase shift is 360/n (where n is the number of channels enabled). ps[6..0] = 7-bit phase shift setting - phase shift between each channel is phaseshift<6:0>/(255*pwmfreq). in direct pwm modes, phase shift between each channel is phaseshift<6:0>/12 .8mhz. note that user must not specify a value that gives >360 shift between first and last channels.
isl97673 20 fn7633.2 october 5, 2012 pwm brightness cont rol register (0x00) the brightness control resolution has 256 steps of pwm duty cycle adjustment. the bit assignment is shown in figure 29. all of the bits in this brightness control register can be read or write. step 0 corresponds to the minimum step where the current is less than 10a. steps 1 to 255 represent the linear steps between 0.39% and 100% duty cycle with approximately 0.39% duty cycle adjustment per step. ?an smbus/i 2 c write byte cycle to register 0x00 sets the pwm brightness level only if the backlight controller is in smbus/i 2 c mode (see table 3a operating modes selected by device control register bits 1 and 2). ?an smbus/i 2 c read byte cycle to register 0x00 returns the programmed pwm brightness level. ?an smbus/i 2 c setting of 0xff for register 0x00 sets the backlight controller to the maximum brightness. ?an smbus/i 2 c setting of 0x00 for register 0x00 sets the backlight controller to the minimum brightness output. ? default value for register 0x00 is 0xff. device control register (0x01) figure 29. descriptions of brightness control register register 0x00 pwm brightness control register brt7 brt6 brt5 brt4 brt3 brt2 brt1 brt0 bit 7 (r/w) bit 6 (r/w) bit 5 (r/w) bit 4 (r/w) bit 3 (r/w) bit 2 (r/w) bit 1 (r/w) bit 0 (r/w) bit assignment bit field definitions brt[7..0] = 256 steps of pwm brightness levels figure 30. descriptions of device control register register 0x01 device control register reserved reserved reserved reserved reserved pwm_md pwm_sel bl_ctl bit 7 (r/w) bit 6 (r/w) bit 5 (r/w) bit 4 (r/w) bit 3 (r/w) bit 2 (r/w) bit 1 (r/w) bit 0 (r/w) pwm_md pwm_sel bl_ctl mode xx0backlight off 001smbus/i 2 c and pwm dimming (dpst) 0 1 1 pwmi controlled pwm dimming 101smbus/i 2 c controlled pwm dimming 1 1 1 backlight on but stays with previous mode selection
isl97673 21 fn7633.2 october 5, 2012 this register has two bits that control either smbus/i 2 c controlled or external pwm controlled pwm dimming and a single bit that controls the bl on/off state. the remaining bits are reserved. the bit assignment is shown in figure 30. all other bits in the device control register will read as low unless otherwise written. ? all defined control bits re turn their current, latched value when read. a value of 1 written to bl_ctl turns on the bl in 4ms or less after the write cycle completes. the bl is ? deemed to be on when bit 3 bl_stat of register 0x02 is 1 and register 0x09 is not 0. ? a value of 0 written to bl_ctl immediately turns off the bl. the bl is deemed to be off when bit 3 bl_stat of register 0x02 is 0 and register 0x09 is 0. ? when smbus/i 2 c mode with dpst is selected, register 0x00 reflects the last value written to it from smbus/i 2 c. ? the default value for register 0x01 is 0x00. fault/status register (0x02) this register has 6 status bits that allow monitoring of the backlight controller?s operating state. bit 0 is a logical ?or? of all fault codes to simplify error detection. not all of the bits in this register are fault related (bit 3 is a simple bl status indicator). the remaining bits are reserved and return a ?0? when read. all of the bits in this register are read-only, with the exception of bit 0, which can be cleared by writing to it. ? a read byte cycle to register 0x02 indicates the current bl on/off status in bl_stat (1 if the bl is on, 0 if the bl is off). ? a read byte cycles to register 0x2 also returns fault as the logical or of thrm_shdn, ov_curr, 2_ch_sd, and 1_ch_sd should these events occur. ? 1_ch_sd returns a 1 if one or more channels have faulted out. ? 2_ch_sd returns a 1 if two or more channels have faulted out. ? a fault will not be reported in the event that the bl is commanded on and then immediately off by the system. ? when fault is set to 1, it will remain at 1 even if the signal which sets it goes away. fault will be cleared when the bl_ctl bit of the device control register is toggled or when written low. at that time, if the fault condition is still present or reoccurs, fault will be set to 1 again. bl_stat will not cause fault to be set . ? the default value for register 0x02 is 0x00. si revision register (0x03) the si revision register has 3 bits that allows up to 8 silicon revisions each. in or der to keep the number of silicon revisions low, the revision field will not be updated unless the part will make it out to the user?s factory. thus, if during the first silicon engineering development process, 2 silicon spins were needed, the revision remains as 0. all of the bits in this register are read-only. ? the default value for register 0x03 is 0xc8. the initial value of rev shall be 0. subsequent values of rev will increment by 1. register 0x02 fault/status register reserved reserved 2_ch_sd 1_ch_sd b l_stat ov_curr thrm_shdn fault bit 7 (r) bit 6 (r) bit 5 (r) bit 4 (r) bit 3 (r) bit 2 (r) bit 1 (r) bit 0 (r) bit bit assignment bit field definitions bit 5 2_ch_sd = two led output channels are shutdown (1 = shutdown, 0 = ok) bit 4 1_ch_sd = one led output channel is shutdown (1 = shutdown, 0 = ok) bit 3 bl_stat = bl status (1 = bl on, 0 = bl off) bit 2 ov_curr = input overcurrent (1 = ov ercurrent condition, 0 = current ok) bit 1 thrm_shdn = thermal shutdown (1 = thermal fault, 0 = thermal ok) bit 0 fault = fault occurred (logic ?or? of all of the fault conditions) figure 31. descriptions of fault/status register
isl97673 22 fn7633.2 october 5, 2012 dc brightness cont rol register (0x07) the dc brightness control register 0x07 allows users to have additional dimming flexibility by: 1. effectively achieving 16-bits of dimming control when dc dimming is comb ined with pwm dimming. 2. achieving visual or audio noise free 8-bit dc dimming over potentially noisy pwm dimming. the bit assignment is shown in figure 33. all of the bits in this register can be read or write. steps 0 to 255 represent the linear steps of current adjustment in dc on the fly. it can also be considered as the peak current factory calibration feature to account for various led production batch variations, but external eeprom settings storing and restoring are required. ?an smbus/i 2 c write byte cycle to register 0x07 sets the brightness level in dc only. ?an smbus/i 2 c read byte cycle to register 0x07 returns the current dc brightness level. ? default value for register 0x07 is 0xff. configuration register (0x08) the configuration register provides many extra functions that users can explore in order to optimize the driver performance at a given application. a direct pwm bit allows direct pwm where the output current follows the same input pwm signal. a pwm-to-dc bit allows users to provide convert pwm input into average dc led cu rrent output with the level that is proportional to the input pwm duty cycle. a bstslewrate bit allows users to control the boost fet slew rate (the rates of turn-on and turn-off). the slew rate can be selected to four relative strengths when driving the internal boost fet. the purpose of this function is to allow users to experiment the slew rate with respect to emi effect in the system. in general, the slower the slew rate is, the lower the emi interference to the surrounding circuits; however, the switching loss of the boost fet is also increased. the fsw bit allows users to set the boost conversion switching frequency between 1.2mhz and 600khz. register 0x03 id register led panel mfg3 mfg2 mfg1 mfg0 rev2 rev1 rev0 bit 7 = 1 bit 6 (r) bit 5 (r) bit 4 (r) bit 3 (r) bit 2 (r) bit 1 (r) bit 0 (r) bit assignment bit field definitions mfg[3..0] = manufacturer id. see ?si revision register (0x03)? on page 21. data 0 to 8 in decimal correspond to other vendors data 9 in decimal represents intersil id data 10 to 14 in decimal are reserved data 15 in decimal manufacturer id is not implemented rev[2..0] = silicon rev (rev 0 through rev 7 allowed for silicon spins) figure 32. descriptions of id register figure 33. descriptions of dc brightness control register register 0x07 dc brightness control register brtdc7 brtdc6 brtdc5 brtdc4 brtdc3 brtdc2 brtdc1 brtdc0 bit 7 (r/w) bit 6 (r/w) bit 5 (r/w) bit 4 (r/w) bit 3 (r/w) bit 2 (r/w) bit 1 (r/w) bit 0 (r/w) bit assignment bit field definitions brtdc[7..0] = 256 steps of dc brightness levels
isl97673 23 fn7633.2 october 5, 2012 the vsc bits allow users to set 3 levels of channel short-circuit thresholds or disable it. the bit assignment is shown in figure 34. the default value for register 0x08 is 0x1f. output channel select and fault readout register (0x09) this register can be read or write; the bit position corresponds to the channel. for example, bit 0 corresponds to ch0 and bit 4 corresponds to ch4 and so on. writing data to this register, it enables the channels of interest. when reading data from this register, any disabled channel and any faul ted out channel will read as 0. this allows the user to determine which channel is faulty and optionally not enabling it in order to allow the rest of the system to continue to function. additionally, a faulted out channel can be disabled and re-enabled in order to allow a retry for any faulty channel without having to power-down the other channels. the bit assignment is shown in figure 35. the default for register 0x09 is 0x3f. register 0x08 configuration register reserved direct pwm pwm-to-dc bstslewrate1 bstslewrate0 fsw vsc1 vsc0 bit 7 (r/w) bit 6 (r/w) bit 5 (r/w) bit 4 (r/w) bit 3 (r/w) bit 2 (r/w) bit 1 (r/w) bit 0 (r/w) bit assignment bit field definitions directpwm forces the pwmi signal to dire ctly control the current source s. note that there is some synchronous delay between pwmi and current sources. pwm-to-dc switches current sources on and varies dc level rather than pwming. bstslewrate[1:0] controls strength of fet driver. 00 - 25% drive strength, 01 to 50% drive strength, 10 -75% drive strength, 11 to 100% drive strength. fsw 2 levels of switching frequencies (0 = 1,200khz, 1 = 600khz) vsc[1..0] 3 levels of short-circuit thresholds (0 = disabled, 1 = 3.6v, 2 = 4.8v, 3 = 5.8v) figure 34. descriptions of configuration register figure 35. descriptions of output channel register register 0x09 output channel register reserved reserved ch5 ch4 ch3 ch2 ch1 ch0 bit 7 (r/w) bit 6 (r/w) bit 5 (r/w) bit 4 (r/w) bit 3 (r/w) bit 2 (r/w) bit 1 (r/w) bit 0 (r/w) bit assignment bit field definitions ch[5..0] ch5 = channel 5, ch4 = channel 4 and so on
isl97673 24 fn7633.2 october 5, 2012 phase shift control register (0x0a) the phase shift control register is used to set phase delay between each channels. when bit 7 is set high, the phase delay is set by the number of channels enabled and the pwm frequency. the delay time is defined by the equation 13: where n is the number of channels enabled, and t fpwm is the period of the pwm cycle. when bit 7 is set low, the phase delay is set by bits 6 to 0 and the pwm frequency. the delay time is defined by equation 14: where ps is an integer from 0 to 127, and t fpwm is the period of the pwm cycle. by default, all the register bits are set low, which sets zero delay between each channel. note that the user should not program the register to give more than one period of the pwm cycle delay between the first and last enabled channels. components selections according to the inductor voltage-second balance principle, the change of inductor current during the switching regulator on time is equal to the change of inductor current during the switching regulator off time. since the voltage across an inductor is: and i l @ on = i l @ off, therefore: where d is the switching duty cycle defined by the turn-on time over the switching period. v d is schottky diode forward voltage that can be neglected for approximation. rearranging the terms without accounting for v d gives the boost ratio and duty cycle respectively as: input capacitor switching regulators require input capacitors to deliver peak charging current and to reduce the impedance of the input supply. this reduces interaction between the regulator and input supply, thereby improving system stability. the high switching frequency of the loop causes almost all ripple current to flow in the input capacitor, which must be rated accordingly. a capacitor with low internal series resistance should be chosen to minimize heating effects and improve system efficiency, such as x5r or x7r ceramic capacitors, which offer small size and a lower value of temperature and voltage coefficient compared to other ceramic capacitors. in boost mode, input current flows continuously into the inductor; ac ripple component is only proportional to the rate of the inductor charging, thus, smaller value input capacitors may be used. it is recommended that an input capacitor of at least 10f be used. ensure the voltage rating of the input capacitor is suitable to handle the full supply range. inductor the selection of the inductor should be based on its maximum current (i sat ) characteristics, power dissipation (dcr), emi susceptibility (shielded vs unshielded), and size. inductor type and value influence many key parameters, including ripple current, current limit, efficiency, transient performance and stability. the inductor?s maximum current capability must be adequate enough to handle th e peak current at the worst case condition. if an inductor core is chosen with too low figure 36. descriptions of phase shift control register register 0x0a phase sh ift control register equal phase phase- shift6 phase- shift5 phase- shift4 phase- shift3 phase- shift2 phase- shift1 phase- shift0 bit 7 (r/w) bit 6 (r/w) bit 5 (r/w) bit 4 (r/w) bit 3 (r/w) bit 2 (r/w) bit 1 (r/w) bit 0 (r/w) bit assignment bit field definitions equalphase controls phase shift mode - when 0, phase shift is define d by phaseshift<6:0>. when 1, phase shift is 360/n (where n is the number of channels enabled). phaseshift[6..0] 7-bit phase shift setting - phase shift between each channel is phaseshift<6:0>/(255*pwmfreq) in direct pwm modes, phase sh ift between each channel is phaseshift<6:0>/12.8mhz note that user must not specify a value that gives >360 shift between first and last channels. t delay t fpwm n ? () = (eq. 13) t delay ps 6 0 xt > , < fpwm 255 () ? () = (eq. 14) v l l i l t ? = (eq. 15) v ( i 0 ) l ? dt s v o v d v i ? ? () = l1 ( d ) t s ? ? ? (eq. 16) v o v i 11d ? () ? = ? (eq. 17) dv o ( v i ) v o ? ? = (eq. 18)
isl97673 25 fn7633.2 october 5, 2012 a current rating, saturation in the core will cause the effective inductor value to fall, leading to an increase in peak to average current level, poor efficiency and overheating in the core. the series resistance, dcr, within the inductor causes conduction loss and heat dissipation. a shielded inductor is usually more suitable for emi susceptible applications, such as led backlighting. the peak current can be derived from the voltage across the inductor during the off period, as expressed in equation 19: the choice of 85% is just an average term for the efficiency approximation. the first term is the average current, which is inversely proportional to the input voltage. the second term is the inductor current change, which is inversely proportional to l and f sw . as a result, for a given switching frequency and minimum input voltage on which the system operates, the inductor i sat must be chosen carefully. at a given inductor size, usually the larger the inductance, the higher the series resistance because of the extra winding of the coil. thus, the higher the inductance, the lower the peak current capability. the isl97673 current limit should also have to be taken into account. output capacitors the output capacitor acts to smooth the output voltage and supplies load current directly during the conduction phase of the power switch. outp ut ripple voltage consists of the discharge of the output capacitor for i lpeak during fet on and the voltage drop due to flowing through the esr of the output capacitor. the ripple voltage can be shown as equation 20: the conservation of charge principle in equation 20 also brings up the fact that during the boost switch off period, the output capacitor is charged with the inductor ripple current minus a relatively small output current in boost topology. as a result, the user needs to select an output capacitor with low esr and enough input ripple current capability. the choice of x7r over y5v ceramic capacitor is highly recommend because x7r capacitor is less sensitive to capacitance change over voltage but the y5v capacitor exhibits very high capacitance coefficient such that its absolute capacitance can be reduced to 10~20% to the rated capacitance at maximum voltage. output ripple v co , can be reduced by increasing co or f sw , or using small esr capacitors. in general, ceramic capacitors are the best choice for output capacitors in small to medium sized lcd backlight applications due to their cost, form factor, and low esr. a larger output capacitor will also ease the driver response during pwm dimming off period due to the longer sample and hold effect of the output drooping. the driver does not need to boost harder in the next on period that minimizes transient current. the output capacitor is also needed for compensation, and, in general one to two 4.7f/50v ceramic capacitors are suitable for netbook to notebook display backlight applications. schottky diode a high-speed rectifier diode is necessary to prevent excessive voltage overshoot, especially in the boost configuration. low forward voltage and reverse leakage current will minimize losses, making schottky diodes the preferred choice. although the schottky diode turns on only during the boost switch off period, it carries the same peak current as the inductor, and therefore, a suitable current rated scho ttky diode must be used. applications high current applications each channel of the isl97673 can support up to 30ma. for applications that need higher current, multiple channels can be grouped to achieve the desirable current. for example, the cathode of the last led can be connected to ch0 to ch2, this configuration can be treated as a single string with 90ma current driving capability. il pk v o ( i o ) 85% ( v i ) 12v i v o ( v i ) l ( v o f sw ) ? ? [] ? + ? = (eq. 19) v co i ( o c o df s ) i ( o esr () + ? ? = (eq. 20) figure 37. grouping multiple channels for high current applications ch0 ch1 ch2 v out figure 38. multiple drivers operation smbclk smbdat en/pwm smbclk smbdat en/pwm smbclk/scl smbdat/sda en
isl97673 26 intersil products are manufactured, assembled and tested utilizing iso9000 qu ality systems as noted in the quality certifications found at www.intersil.com/design/quality intersil products are sold by description only. intersil corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, th e reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accura te and reliable. however, no re sponsibility is assumed by inte rsil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which ma y result from its use. no licen se is granted by implication o r otherwise under any patent or patent rights of intersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn7633.2 october 5, 2012 for additional products, see www.intersil.com/product_tree multiple drivers operation for large lcd panels where more than 6 channels of leds are needed, multiple isl97673s with each driver having its own supporting components can be controlled together with the common smbus/i 2 c. while the isl97673 does not have extra pins strappable slave address feature, but a separate en signal can be applied to each driver for asynchronous operation. a trade-off of such scheme is that an exact faulty channel cannot be identified since both ics have the same i2c slave address. products intersil corporation is a leader in the design and manuf acture of high-performance analog semiconductors. the company's products address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks. intersil's product families address power management and analog signal processing functions. go to www.intersil.com/products for a complete list of intersil product families. for a complete listing of applications, related documentat ion and related parts, please see the respective product information page. also, please check the product information page to ensure that you have the most updated datasheet: isl97673 to report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff fits are available from our website at http://rel.intersil.com/reports/search.php revision history the revision history provided is for informat ional purposes only and is believed to be accurate, but not warranted. please go t o web to make sure you have the latest rev. date revision change august 1, 2012 fn7633.2 on page 12, change d 401.8 to 410.5 in equations 2 and 4. july 18, 2012 fn7633.1 stamped page 1 ?not recommended for new designs? june 24, 2010 fn7633.0 initial release.
isl97673 27 fn7633.2 october 5, 2012 package outline drawing l20.3x4 20 lead quad flat no-lead plastic package rev 1, 3/1 0 typical recommended land pattern detail "x" top view bottom view side view located within the zone indicated. the pin #1 indentifier may be unless otherwise specified, tolerance : decimal 0.05 tiebar shown (if present) is a non-functional feature. the configuration of the pin #1 id entifier is optional, but must be between 0.15mm and 0.30mm from the terminal tip. dimension applies to the metallized terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing conform to amse y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: 0.10 m c a b mc 0.05 0.15 0.08 c 0.10 c a b c c 4.00 3.00 20x 0.400.10 2.65 1.65 0.25 0.50 (2.80) (1.65) +0.10 -0.15 +0.10 -0.15 +0.05 -0.07 20x a a 4 (4x) seating plane 0.9 0.10 5 0.2 ref 0.05 max. see detail "x" 0.00 min. (c 0.40) 1 20 17 16 11 6 10 7 (3.80) (2.65) (20 x 0.25) (20 x 0.60) (16 x 0.50) 16x view "a-a" pin 1 index area pin 1 index area 6 6

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